Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
Qwenputer is an experimental model featuring a deterministic RISC-V CPU embedded within its weights. This CPU utilizes Gated DeltaNet attention layers as RAM, running arithmetic operations, C, and MicroPython code during forward passes without external runtime or tool usage. It is not a plugin, tool, or sandbox. The GDN layers act as RAM, with each head keeping a state matrix that updates using the delta rule.
By setting the gate to 1 and beta to 1, the RNN forgets stored information at a controlled rate, enabling the GDN to function as RAM. A one-hot key encoding system allows the CPU to overwrite and retrieve exact values from the state matrix. This modification turns the GDN layers into RAM, reducing costs compared to using normal attention as RAM.
The CPU is a 32-bit RISC-V core (RV32IM, plus Zba extension and a small bignum unit) and is integrated into the model's weights, passing the official riscv-tests and running 18 million instructions without error. The CPU can also run C and MicroPython code in the forward passes, adding a filesystem on top of the weights for additional functionality.
The CPU operates entirely internally, and Qwen3-Next and Qwen 3.5 models can use it efficiently without post-training adjustments.
Written by urgent.news from Hacker News's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
