Microsoft's Maia 300 Publishes Rack Numbers for Its Own Inference Silicon
TL;DR Microsoft Azure Maia 300 is an AI inference accelerator, the third generation of Microsoft's own chip family for running large models inside its datacenters, announced on 12 October 2026. The chip is a multi-chiplet package with compute chiplets on TSMC's N2P process, memory-controller and I/O functions on separate dies, eight HBM4 stacks providing 288 GB and 18.0 TB/s of peak bandwidth…
Microsoft has announced its latest AI inference accelerator, the Maia 300, as part of its Azure Maia chip family. This is the third generation chip from Microsoft, designed for running large models inside datacenters. The chip is a multi-chiplet package featuring compute chiplets on TSMC's N2P process, memory-controller and I/O functions on separate dies.
It packs eight HBM4 stacks, providing 288 GB of memory and 18.0 TB/s of peak bandwidth. The system consumes a total of 167 kilowatts of power, providing an impressive 27.6 TB of HBM memory and 1.7 PB/s of aggregate memory bandwidth. This represents a significant increase in accelerator density compared to its predecessor, Maia 200, with 96 accelerators housed in the rack.
The new chip supports enhanced MXFP4 and sub-3-bit storage formats, and is expected to deliver 40% more tokens per megawatt and up to 7x the rack-scale token throughput of Maia 200. Microsoft's Maia 300 is currently in production and will be deployed in datacenters across the United States, Europe, and Australia, replacing its existing Maia 200 in these facilities.
Written by urgent.news from Dev.to's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
