Samsung teases new HBM5 with twice the performance of HBM4E —ambitious data transfer rates could hint at 4,096-bit interface
Samsung expects HBM5 to deliver 4 TB/s of bandwidth per stack by late 2020s, which will enable AI accelerators with aggregated memory bandwidth of around 100 TB/s.
Samsung has unveiled plans for the next-generation HBM5 memory specification, aiming to double the performance and enhance power efficiency compared to HBM4E. At the Memory Executive Summit, preceding Semicon Taiwan 2026, Samsung's head of product planning, Choi Jang-seok, revealed that HBM5 will feature a 4,096-bit interface. This ambitious move could potentially lead to peak bandwidth of around 4 TB/s per stack in 2028-2029.
While HBM4E has a JEDEC transfer rate of 12 GT/s, Samsung believes HBM5 must either double this rate to 24 GT/s, widen the interface to 4,096 bits, or combine both for optimal performance. The broader interface, however, raises concerns about increased complexity in terms of base die, drivers, receivers, and routing. Despite the challenges, the aggressive target sets the stage for significant advancements in memory bandwidth in the coming years.
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