Hot Chips 2026: Samsung reveals a three-phase HBM roadmap that puts logic and compute inside memory — zHBM ultimately stacks DRAM directly on top of the processor

Samsung has introduced a three-part plan to evolve high-bandwidth memory (HBM) into a system that combines memory and computing capabilities, leading to Samsung's "zHBM" architecture. At the Hot Chips 2026 conference, Sangwook Han of Samsung's DRAM design team detailed the roadmap, starting with reclaiming space for the processor (XPU).

The first phase involves removing non-computing elements from the HBM base die, such as the HBM Physical Interface (PHY), and relocating them to the base die's unused silicon. This process reduces the size of the PHY and the memory controller, saving power and enabling new features like direct memory expansion and integrated sensors.

The second phase expands the base die's capabilities by adding additional features like self-test hardware, memory telemetry, and computational elements onto the die. The third and final phase, called "zHBM," represents a fully 3D approach where the processor is placed beneath the memory. This advanced architecture aims to minimize traffic across the interposer, lower latency, and reduce I/O power consumption.