Hot Chips 2026: Cerebras lays out the future of wafer-scale AI — Nexus system architecture triples rack-scale performance, CS-6 wafer to incorporate stacked DRAM

Hot Chips 2026 showcased Cerebras' innovative wafer-scale accelerator roadmap, highlighting the performance benefits of its upgraded Nexus rack design. The CS-4 rack-scale accelerator utilized three WS-3T wafer-scale engines, each containing 44GB of memory. However, as model sizes and contexts continue to grow, memory demands increase, posing challenges for traditional GPU makers.

To address these issues, Cerebras is exploring a new approach with its CS-6 system, incorporating stacked designs for wafer-scale engines. By integrating stacked DRAM on top of its logic and SRAM wafer, Cerebras aims to maintain its performance lead in inference while reducing the chip's overall area. This ambitious strategy allows for the potential increase in the number of WSEs produced, which could help alleviate constraints as wafer demand grows.

In the present, Cerebras is enhancing its existing wafer-scale platform with the CS-4 rack-scale system and its innovative Nexus rack design. The CS-4 incorporates three refreshed WS-3T wafers into self-contained "backpacks" that include power delivery, scale-up networking, and liquid cooling infrastructure. The Nexus design disaggregates the WSE's I/O interfaces from the rest of the backpack's components, providing RoCE v2 RDMA connections and direct connections between wafers in the rack.

This modular design enables easy upgrades and reduces the number of cables connecting the system, simplifying maintenance and minimizing potential points of failure.

The Nexus rack design features up to 10 power delivery units per backpack, allowing for varying levels of redundancy based on the operator's needs. By mounting the wafer-scale engines vertically in these backpack modules, Cerebras eliminates the need for a PCB or substrate to handle supporting infrastructure. Instead, a large copper busbar delivers power directly to the chip, minimizing power losses and translating these savings into increased performance.

Each WS-3T delivers twice as many sparse FP16 petaFLOPS and twice as much memory bandwidth from its SRAM compared to the WS-3, while still utilizing the same base silicon. However, the WS-3T is limited to 44GB of memory across the entire wafer, with a CS-4 rack providing only 132GB in total. As model sizes and demands continue to evolve, Cerebras must continue to scale up and out to meet these challenges, setting the stage for a new era in AI wafer-scale accelerators.