RISC-V: They should have known better

RISC-V enthusiasts claim the architecture will dominate both high-end CPUs and tiny microcontrollers, but this is unrealistic. High-end CPUs require complex features, while microcontrollers need simplicity and low cost. RISC-V's design choices reflect this divide, making it less suitable for either extreme. In microcontrollers, interrupt latency and code size are crucial, while high-end CPUs prioritize performance and complex arithmetic.

RISC-V lacks interrupt handling mechanisms found in cores like the Cortex-M0, resulting in significantly slower interrupt processing. The architecture's compressed instructions are also poorly designed, with limited offset ranges and unintuitive encoding. Despite these drawbacks, RISC-V may excel in the ultra-cheap single-use microcontroller market, eventually displacing 8051 cores.

However, its lack of standard extensions undermines the intended standardization, creating fragmentation in the market.