RISC-V: They should have known better

The RISC-V architecture has garnered mixed reactions, with some praising its brilliance while others criticize its lack of versatility. One key issue is that RISC-V cannot excel in all use cases due to its design choices, which often directly impact the CPU architecture. While it is expected to dominate the low-cost single-use microcontroller space, this advantage comes at the expense of its microarchitectural limitations.

In the realm of microcontrollers, interrupt latency and code size are crucial factors. RISC-V struggles in these areas, requiring at least 44 cycles for interrupt handling compared to the Cortex-M0's 27-cycle cost. This significant difference is due to the lack of hardware support for interrupt stacking in RISC-V, forcing vendors to resort to non-standard silicon designs. This, in turn, further fragment the ISA, making it weaker than it could be.

Another aspect of RISC-V is its compressed instruction set, which is considered poorly designed. For example, storing a byte to a register plus offset has a limited range of options, and even the halfword store instruction is less efficient compared to other architectures. These design choices contribute to the overall inferiority of RISC-V in comparison to established technologies like the Cortex-M0.