AMD's Epyc X-chips are back after a three-year hiatus

AMD's Epyc X-chips are returning after a three-year absence. These cache-packed chips, based on the House of Zen's frequency-optimized SKUs, will offer up to 96 cores and utilize the company's 3D V-Cache chip stack technology to triple the L3 cache density to over a gigabyte. However, these Venice-X chips won't be shipping until the second half of 2027.

Primarily targeted at latency-sensitive technical and scientific computing workloads, such as computational fluid dynamics and electronic design automation, AMD relies heavily on its X-series Epycs for such tasks. AMD Fellow Phil Steinke explained that keeping more of the model in cache allows CPU cores to avoid waiting as long for data to move in and out of system memory.

Unlike previous cache expansions that required larger chiplets with lower yields, AMD's advanced packaging technique gives CPU dies a small SRAM backpack. This technology, first introduced in the Ryzen 7 5800X3D in 2022, has been used in AMD's Milan generation of Epycs to expand L3 cache capacity. The return of the X-chips follows AMD's decision not to launch an X-series chip every generation, as this market tends to have a slower cadence.

The Venice-X chips feature the same recipe as their predecessors, with each up to eight CPU dies bonded to a 96 MB SRAM tile, totaling 144 MB of L3 per chiplet or 1,152 MB per socket. While core count and cache capacity have remained the same, clock speeds have increased, with Venice-X now hitting 5.3 GHz compared to Genoa-X's 3.7 GHz.

The integration of the SRAM tile required a trade-off, as it initially limited boost clocks due to heat buildup. However, by moving the SRAM tile to the bottom of the stack, AMD has enabled these chips to run hotter and faster. AMD believes that the Venice-X chips may find wider adoption in HPC compared to previous generations, as customers can now choose between larger caches and higher clock speeds.