SK Hynix Says Memory Hierarchy Must Be Optimized
Ahn Hyun, president and head of development at SK hynix, said in a keynote speech at ‘SEDEX 2026’ held on October 14 that the rapid expansion of the AI inference market is creating a new memory bottleneck. He stressed that, to address this, a strategy of optimizing the entire memory hierarchy is ess
SK hynix's President Ahn Hyun highlighted the necessity of a comprehensive memory hierarchy optimization during his keynote speech at SEDEX 2026, held on October 14. He emphasized that the growing AI inference market, characterized by escalating workload complexity, context length, and inference request volume, has introduced a new memory bottleneck that extends beyond improving individual product performance.
Ahn pointed out that the demand for 'KV cache' capacity, enabling AI to reuse previous data, has led to increased data movement between multiple layers, ranging from HBM to SSD. This has resulted in a widening performance gap between different memory tiers and the movement itself, which has now emerged as the primary challenge. To overcome this hurdle, SK hynix intends to further subdivide and diversify their memory architecture.
In an attempt to narrow the performance gap between existing SRAM and HBM, the company is focusing on '3D Stacked DRAM' technology, which directly stacks DRAM on top of logic semiconductors such as GPUs and NPUs. This architecture aims to significantly reduce the physical distance between processors and data, enhancing performance while simultaneously reducing energy consumption.
Additionally, SK hynix showcased 'HBF' (High Bandwidth Flash), a next-generation memory technology that integrates HBM stacking technology with NAND flash. Positioned between HBM and DRAM, HBF is designed to deliver approximately half the bandwidth of same-generation HBM while providing roughly ten times the capacity. Aimed at addressing the read-intensive nature of AI inference, HBF is considered a strategic solution to enhance system efficiency.
Furthermore, SK hynix is contemplating transitioning HBM into 'custom HBM', which will be tailored for each customer's AI system, featuring a memory controller and customer-specific logic directly on the base die. This approach aims to create an optimal architecture that surpasses the limitations of traditional storage solutions.
Leveraging their expertise developed from HBM1 through HBM4E, SK hynix plans to broaden their memory ecosystem by integrating CXL with upcoming storage technologies. Meanwhile, the company positioned itself as a leader in the AI memory landscape by setting up its largest booth at the exhibition and unveiling an extensive array of their latest AI memory solutions.
These offerings included an HBM wafer signed by NVIDIA CEO Jensen Huang, 6th-generation 10-nanometer-class DRAM, and enterprise SSDs equipped with liquid cooling capabilities. SK hynix affirmed their commitment to driving sustained growth in the AI era by adopting a proactive strategy of standardizing HBF and collaborating with global partners.
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