‘This is how AI should be used’ — OpenAI head of hardware breaks down the AI-assisted design of its Jalapeño ASIC
OpenAI says AI-assisted Jalapeño chip design "established a new baseline" for the industry, and there is already a lot of interest from others to learn how the company pulled it off.
OpenAI's head of hardware, Richard Ho, has outlined how the company designed its new AI-assisted Jalapeño ASIC, which represents a significant departure from traditional chip design timelines. The AI played a pivotal role in both the hardware and software co-design, enabling the ASIC to transition from RTL to tapeout in just nine months, a record-breaking timeframe.
This development, Ho suggests, has set a new industry standard - previously, developing a chip typically took 18 to 24 months. Despite the use of advanced AI models, Ho emphasized the paramount importance of skilled engineers in guiding these systems, stating that the Jalapeño development is a model for how engineering teams should operate in the AI era.
The company utilized its own internal AI models, including Codex and Sol, and even newer models like Astra, which have shown marked improvement since the project's inception in November 2025. While the use of AI expedited the process, the team still faced challenges, such as the B0 stepping of Jalapeño reportedly delivering a 25% improvement in performance per watt, which is a significant leap over the original A0 stepping.
OpenAI's innovative approach has caught the attention of other industry players, with former hardware engineer Clive Chan joining Anthropic. The company may explore ways to productize its AI chip design workflow, potentially leveraging its upcoming models, like GPT-6 Astra, to aid other firms in this field.
Written by urgent.news from Tom's Hardware's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
