China's CXMT hits 12nm-class DRAM milestone — new 5th-gen DRAM tech uses quadruple-patterning to boost die capacity by 50%

China's DRAM leader, CXMT, has commenced mass production utilizing its cutting-edge 5th-generation DRAM process technology, codenamed G5. This groundbreaking advancement reduces DRAM's active-area half-pitch to 11.95nm through a sophisticated quadruple-patterning lithography method. While this milestone brings CXMT closer to 10nm-class DRAM technologies, it does not directly translate into a conventional node designation.

In addition to this, CXMT's DRAM-optimized high-K metal gate (HKMG) process has successfully decreased the height of the core cell array to 6,762nm. To further enhance storage capacitors, the company implemented process modifications and incorporated new materials, achieving an impressive depth-to-width aspect ratio of approximately 45:1. This remarkable ratio allows for reduced DRAM cell area, enabling the fitting of more memory arrays onto a wafer and ultimately increasing retail capacity.

The first CXMT devices to be mass-produced using the G5 technology are 24Gb LPDDR5X chips, already deployed in mainstream Chinese flagship smartphones. These new chips boast a 50% higher capacity compared to CXMT's previous models. However, there are several key caveats to consider. Firstly, CXMT's 11.95nm active-area half-pitch is not a standard node designation, causing simplification.

Secondly, the disclosed dimensions do not equate to technological parity with leading DRAM processes from Micron, Samsung, and SK hynix. Thirdly, CXMT has not disclosed yields, making it impossible to determine productivity improvements, known-good dies, or the actual manufacturing cost per bit. Despite these complexities, CXMT's achievement in 11.95-class DRAM node production is a significant milestone.