A preview of the future Intel Architecture documentation

This website provides a preview of how Intel plans to document and present the Intel® Architecture in the future. The goal is to create a specification that is more accurate and accessible than the current "SDM" (Intel® 64 and IA-32 Architectures Software Development Manual). Users are encouraged to provide feedback on the usability, accessibility, and any issues they encounter while using the preview.

The new website format aims to improve searchability and exploration of the architecture. It will be used alongside the existing PDF format. The specification language enables testing, making the specification more precise and accurate. Instruction encoding tables on each instruction page present additional information and are displayed differently from the current SDM.

The preview includes almost all instructions documented in the SDM, with the notable omissions being instructions associated with certain features. While a significant effort has been made to test the specification, it has not been completely tested, and further testing is planned. Data processing instructions are relatively easy to test, while code containing branches like privilege level changes and exception handling poses more challenges.

The SDM remains the official specification of the architecture, and the goal is to have a completely accurate specification. However, due to the incomplete nature of the specification, users should not rely on its accuracy at this stage. There is a risk of "overspecification," where a specification becomes inconsistent with future processor behavior. Code review is employed to minimize this risk, but future amendments may be necessary.

Future releases will expand the specification to cover more instructions, underlying architecture aspects like exceptions, memory paging, and modes, and will have fewer bugs. The documentation will be updated as the architecture evolves with new features. User input is sought on priorities, such as focusing on commonly used features or recently added ones like APX, AVX10, and ISE.

The desired balance between executable specifications of instructions and features versus details of MSRs (Model-Specific Registers) and CPUID (Central Processing Unit Identification) is also of interest.