Samsung showcases chip 3D architecture strategy at SEMICON Taiwan
Samsung Electronics on Tuesday showcased its 3D architecture strategy to break through current limitations in memory chip manufacturing during SEMICON Taiwan 2026, an international exhibition covering semiconductor design, manufacturing, testing and packaging. According to the company, Samsung Electronics Device Solutions Vice President Choi Jang-seok delivered a keynote speech at the Memory…
Samsung Electronics presented its innovative 3D architecture strategy at the SEMICON Taiwan 2026 exhibition, aiming to overcome current constraints in memory chip manufacturing, according to the company's Device Solutions Vice President Choi Jang-seok. On Tuesday, Choi delivered a keynote address at the Memory Executive Summit, an introductory event for SEMICON Taiwan 2026, set to commence on Wednesday.
Choi emphasized Samsung's pursuit of advancing memory technology through its "CUBE" strategy, which integrates 3D technologies into various manufacturing processes to enhance capacity, utilization, bandwidth, and efficiency. In memory chips, 3D architecture involves stacking chip dies or other components vertically, thereby reducing the distance data must traverse, expanding data pathways, and enhancing energy efficiency.
This approach is dubbed 3D architecture because the chips or memory dies are arranged vertically rather than side by side on a two-dimensional surface. High-bandwidth memory (HBM) is noted as an application of this technology.
Written by urgent.news from The Korea Times's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
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