Hot Chips 2026: Intel details cutting-edge tech in entry-level Wildcat Lake — value-focused 18A chips necessitated UCIe integration
Intel's Wildcat Lake is competing in the budget laptop market, but it takes a very different approach, leveraging a UCIe interconnect and Intel's latest 18A node.
Intel's Wildcat Lake, a budget-focused processor, debuted in 2026 with a focus on cutting-edge technology while remaining cost-effective. This new architecture was heavily influenced by the Universal Chiplet Interconnect Express (UCIe) standard, which Intel and AMD had been supporting since its inception in 2022. UCIe played a crucial role in minimizing costs and enabling Wildcat Lake's existence in the first place.
To achieve a budget part, Intel opted for a Multi-Chip Package (MCP) design rather than a monolithic design or an advanced 2.5D and 3D packaging. This decision allowed Intel to utilize its latest and most expensive IP cores for compute and integrate them into a budget domain. The compute die of Wildcat Lake utilized 18A process technology, while the I/O die featured Intel's latest I/O technology (ISMC's N6).
A key innovation in Wildcat Lake was the increased UCIe interconnect area, which was 70% larger than that on the prior-generation Panther Lake. However, this larger interconnect came with increased power demands, particularly in idle systems without panel self-refresh. To address this, Intel implemented a buffer before the UCIe link to hold panel refreshes, thereby reducing power consumption.
Trimming down the compute die was a significant aspect of Wildcat Lake's cost-cutting strategy. Intel removed four Xe cores, dropped the dedicated ray tracing accelerator, reduced the number of NPU tiles from three to one, and downsized the memory subsystem to a 64-bit bus. These changes resulted in a 38% reduction in die space for the compute die.
On the I/O die, Intel eliminated the camera PHY, reduced PCIe and USB support, and slimmed down the audio engine, all of which contributed to a 15% decrease in die area. The camera controller's responsibility was shifted to the OEMs. The UCIe version 3.0 supported up to 64 GT/s data rates, but Intel capped the transfer rate at 8 GT/s to maintain stability and reduce bit-rate errors. This reduced data rate helped Intel save costs by eliminating unnecessary bit-correction systems.
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