RISC-V 32-bit: What does GCC do? (Part 1)
1. Introduction and Problem Statement A good way to learn what a compiler really does when transforming C source code into a binary is to disassemble the binary and compare it with the C source code. While this was traditionally true for 8-bit microcontrollers, it is equally insightful for modern 32-bit RISC architectures like RISC-V (RV32I). To test our 32-bit toolchain (GCC / Clang-LLVM), we…
RISC-V 32-bit, also known as RV32I, is an open-standard Instruction Set Architecture designed around strict Load-Store RISC principles. In this variant, there are 32 general-purpose 32-bit registers, which makes register allocation and compiler optimizations more straightforward compared to 8-bit systems. The core registers include x0 (zero), x1 (ra), x2 (sp), x3 and x4 (gp and tp), x5 to x7 and x28 to x31 (t0 to t6), x8 (s0/fp) and x9, x18 to x27 (s1 to s11), a0 and a1 (function arguments/return values), and PC (Program Counter).
Unlike many other architectures, RISC-V does not have dedicated condition flag registers. Instead, conditional branches directly compare two registers, which eliminates hidden pipeline state dependencies.
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