Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute
One hardware researcher, Christopher Domas (@xoreaxeaxeax on GitHub), is taking a different approach with the CPU Deoptimization leaderboard, which looks not to make Assembly instructions run as fast as possible, but as slow as possible to find the single instruction with the highest latency.
Hardware researcher Christopher Domas has embarked on a project to identify the slowest single x86 instruction, creating a hall of shame showcasing the worst offenders. The winner of this endeavor is the fxrstor64 instruction, which took an astonishing 62 seconds, or over 198 billion cycles, to complete its task. Domas achieved this by first locating a high-latency area in the internal PCIe fabric, then forcing the CPU to load a 512-byte state from Memory-Mapped I/O, essentially processing all those 512 bytes at their slowest possible pace.
To further extend the execution time, he depleted the fabric while the load was in flight, overwhelming the CPU's PCIe root complex and causing the state restore to queue behind frivolous read operations. The next step in the project is to employ the AMX instructions available in Intel's Sapphire Rapids, which could potentially cause the instruction to hang for more than 1 trillion cycles.
Domas has also planned ARM and RISC-V leaderboards, and the x86 leaderboard is now available on GitHub. The project aims to shed light on the slowest machine instructions, rather than optimizing for speed, and the rankings are based on how you manipulate the instruction rather than the instruction itself.
Written by urgent.news from Tom's Hardware's reporting — not their text. Machine-written — it may contain errors, so check the original before relying on it.
