Samsung unveils industry's 1st zHBM concept, targeting 8-fold HBM5 performance

Samsung Electronics unveiled industry-leading concepts of zHBM, a revolutionary next-generation memory architecture, on Aug. 5, promising approximately eight times the performance of HBM5. The unveiling took place at the Future of Memory and Storage 2026 conference in Santa Clara, California. Tailored for advanced AI computing, zHBM boasts a novel memory architecture where high-bandwidth memory (HBM) is vertically stacked above AI accelerators, a departure from traditional designs where HBM is placed alongside the processor.

Utilizing wafer-bonding technology, zHBM achieves memory density more than ten times that of HBM5, while also delivering triple the energy efficiency and reducing thermal resistance by over 50%. The technology further allows for customized designs by integrating customer-specific intellectual properties into the interlayer between memory and the AI accelerator, thereby enhancing memory capacity and AI accelerator performance.

By cutting the distance data travels between AI processors and memory, zHBM is engineered to provide higher bandwidth and greater power efficiency, essential for the rapid data processing required in large-scale AI training and inference. Samsung Electronics, collaborating closely with customers, aims to further refine AI processor and memory integration through zHBM to maximize AI system performance.