Co-Packaged Optics (CPO) foundry roadmaps — breaking down TSMC, Intel, Samsung, and GlobalFoundries' approach to next-generation scale-up connectivity
As AI systems outgrow copper interconnects, TSMC, Intel, Samsung Foundry, and GlobalFoundries are pursuing four distinctly different co-packaged optics strategies to bring optical connectivity closer to compute.
TSMC, Intel, Samsung Foundry, and GlobalFoundries are the four foundries currently working on co-packaged optics (CPO) manufacturing strategies. TSMC, in particular, has developed the Compact Universal Photonic Engine (COUPE) to bring optical interconnects closer to processors, addressing the limitations of electrical interconnects as AI workloads increase.
COUPE's progress can be broken down into three stages: COUPE on PCB, COUPE on substrate, and COUPE on interposer. The COUPE on PCB phase involves bonding a COUPE with a photonic integrated circuit (PIC) using SoIC-X bonding technology to create 1.6 Tbps bandwidth solutions. The COUPE on substrate phase integrates COUPE with advanced packaging technology, enabling motherboard-level optical interconnects with up to 6.4 Tbps bandwidth, 2x power efficiency, and 10x lower latency.
TSMC's COUPE on interposer phase, currently in the exploratory stage, aims to integrate a 12.8 Tbps optical engine directly into the processor package, offering 5x power efficiency and 20x lower latency. This architecture could be particularly attractive for hyperscalers building clusters with thousands of accelerators.
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