A deep dive into Nvidia's Vera CPU and the Olympus cores that power it

On Tuesday, Nvidia unveiled Vera, its first custom CPU design aimed at challenging Intel and AMD's dominance in the CPU market. The new chip is set to be deployed by a range of hyperscalers and cloud providers, including Alibaba, ByteDance, Meta, Oracle, CoreWeave, Lambda, Nebius, and NScale. Vera boasts 88 Armv9.2 cores, 176 threads, and support for up to 1.5 TB of LPDDR5X memory, with the ability to operate as a standalone platform independent of Nvidia's GPUs.

The chip's architecture is designed to address pipeline and execution bottlenecks, making it more effective for managing GPUs in new Vera Rubin systems and hosting AI agents, which run independently of GPUs. Unlike AMD's multi-die approach, Vera's compute die is monolithic, with all 88 cores housed on a single silicon chip fabricated on TSMC's 3nm process.

Nvidia's monolithic compute architecture aims to improve core-to-core bandwidth and latency compared to competitors. Surrounding the compute die are eight LPDDR5x controllers and two I/O dies, one for PCIe 6.4 and CXL 3.1 connectivity and another for NVLink Chip-to-Chip interface. The chip is packaged similarly to Amazon's Graviton 4 CPUs, with a monolithic compute die and disaggregated I/O and memory functionality.

At the heart of Vera is its own ARMv9.2-compatible core called Olympus. While Olympus is heavily based on existing Arm IP, Nvidia claims several customizations to optimize the chip for specific workloads. One notable feature is Olympus' neural branch predictor, which can explore two code branches simultaneously, potentially increasing performance for branch-heavy workloads like AI code assistants.

Nvidia also implemented memory renaming and value prediction schemes to further reduce pipeline stalls and improve instruction per clock (IPC) performance.