Strata — memory is explicit I/O
I've long thought about how we're influenced by CPU architectures, and importantly, their ISAs. In a discussion at a meetup, I brought up a topic that interested me for a while: how would an ISA that exposes memory and cache interactions in a more explicit way (because if you think about it, memory is very much I/O), as opposed to being smart and predictive on its own? An obscure interest, of…
We haven't written up this one. Lobsters has the full story — the link below goes straight to it.
