An Epyc trip to Venice: Everything we do and don't know about AMD's 256-core monster chip
16 channels of DDR5, 5 GHz clock speeds, and support for CXL 3.1 memory god boxes? What's not to like?
In a recent release, AMD unveiled its Venice Epyc chips, marking a major architectural shift for the chipmaker since the debut of Rome in 2019. These new 6th-gen Zen-based CPUs are set to be the most diverse CPU portfolio ever, covering general purposes, HPC, AI, and eventually consumer platforms.
While AMD has not revealed all the details about the 6th-gen Zen cores, the whitepaper released by AMD aims to counter Nvidia's narrative around its Vera CPUs. The whitepaper provides some additional insights into the performance claims made in the paper.
AMD's Venice lineup can be categorized into four main groups: high-performance, enterprise, HPC, and AI. The performance-optimized parts will be the ones actually released in 2026, while the rest will follow in 2027.
The Epyc 9006 SP7 platform, AMD's main focus for the past year, will offer up to 256 cores, 16 channels of DDR5, and 128 lanes of PCIe 6.0 connectivity. However, Venice comes in two distinct flavors: density-optimized and frequency-optimized parts. The 256-core version is the density-optimized part, while there is also a 96-core part capable of boosting to 5 GHz.
The 256-core Venice part features a pair of I/O dies surrounded by eight core-complex dies (CCDs), doubling the number of compute cores per chiplet to 32 and quadrupling the shared L3 cache from 32 MB per chiplet to 128 MB. This results in a gigabyte of L3 onboard for fully loaded Venice CPUs.
In comparison to the frequency-optimized parts, AMD has only increased core counts and L3 caches by about 50% over the last generation, with 12 cores and 48 MB of L3 per chiplet. One of the notable changes in Venice is the cache hierarchy, with no difference between Zen 6C cores and Zen 6 cores aside from clock speeds.
AMD has also included two I/O dies in Venice, connecting the CCDs with PCIe 6.0 connectivity, which is twice as fast compared to the previous generations. Additionally, Support for CXL 3.1 connectivity allows customers to take advantage of memory god boxes to pool and share memory between them. The faster I/O and added support for 16 channels of DDR5 memory provide Venice with a whopping 1.6 TB/s of memory bandwidth.
Written by urgent.news from The Register Science's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
