ASML targets 2033 for High-NA EUV with larger masks, promising a 40% productivity gain

ASML is collaborating with customers to develop a larger mask format for its upcoming High-NA EUV lithography tools. This change could enable the systems to be more beneficial for manufacturing the largest AI and data center chips. ASML's current EUV machines can produce chips up to approximately 800 square millimeters in size, which is sufficient for components designed by companies such as Nvidia and Google.

High-NA EUV technology can create finer features than current EUV tools, aiding chipmakers in developing denser designs at advanced nodes; however, its smaller mask size restricts the die area that can be printed in a single exposure. To tackle this limitation, ASML intends to transition to a 12-inch mask format for High-NA EUV.

This larger mask would permit the new machines to handle chips as big as the most substantial data center devices produced with existing EUV equipment. ASML anticipates demonstrating a pilot line with the larger masks by 2031 and aims to have the technology ready for high-volume production by 2033. The company emphasizes the need for cooperation from customers and other industry partners to make this transition successful.

ASML's Chief Technology Officer, Marco Pieters, stated that if the industry collaborates effectively, the productivity of these systems could increase by 40%. The initiative aims to broaden the appeal of High-NA EUV, which is anticipated to be more costly and technically challenging than the current generation of EUV equipment. Despite offering improved resolution, chipmakers also require sufficient wafer output to justify using these tools in volume production.

SK Hynix is evaluating whether to join the consortium working on the introduction of 12-inch masks, with plans to utilize High-NA EUV processes in mass production of DRAM chips by 2028. Samsung intends to commence using High-NA EUV for high-volume DRAM production in 2028, while TSMC anticipates introducing the technology in high-volume manufacturing of advanced-node chips starting in 2030.

These timelines indicate that High-NA EUV is progressing from its initial stages towards broader production planning. ASML's focus on larger masks addresses another issue: ensuring the technology can support the oversized chips increasingly utilized for AI systems and cloud infrastructure.