3 Common STM32 Timer Mistakes That Give You the Wrong PWM Frequency
The symptom: PSC and ARR look right, but the frequency is wrong STM32 timer math is compact enough to fit in one line, yet small assumptions can move a PWM output far from its target. Before changing firmware at random, check the timer clock, the register offsets, and the way you chose PSC and ARR. The examples below use an up-counting, edge-aligned time base. Mistake #1: forgetting both “+1”…
Many STM32 timer setups yield incorrect PWM frequencies despite correct initial values for PSC and ARR. To avoid this, verify three key elements: the timer clock, the register offsets like PSC and ARR, and the calculations for PSC, ARR, and duty cycle.
In up-counting edge-aligned mode, the formulas are: counter clock = timer clock / (PSC + 1), PWM frequency = timer clock / ((PSC + 1) * (ARR + 1)), and duty = CCR / (ARR + 1) * 100%. Remember to add the "+1" terms, which are crucial in the equations.
Firstly, forget the "+1" terms when calculating counter clock and PWM frequency. Using PSC=71 without adding 1 is incorrect; it should be divide-by-72 instead of divide-by-71. Similarly, a 0-999 ARR counter counts 1000 ticks, not 999.
Secondly, ensure the correct timer input clock. The CPU frequency isn't automatically the timer's input clock. Look at the clock tree for the APB bus and prescaler, then determine the effective clock given to the timer. Some families multiply the timer clock when using non-1 APB prescalers, so treat this as a device-specific rule.
Lastly, PSC and ARR form a pair. There are multiple integer pairs that can give the same frequency but differ in counter rate and duty-cycle resolution. PSC determines the counter clock after prescaling, while ARR sets the number of counter ticks in a period. CCR sets the compare point. Choosing valid PSC and ARR values is a design decision, not a guess. A larger ARR offers more duty resolution, but both PSC and ARR must fit the timer width and CCR's range.
For example, with a 72 MHz timer clock and aiming for 1 kHz PWM, use PSC=71, ARR=999, and CCR=250. This yields a counter clock of 1 MHz, a PWM frequency of 1 kHz, and a duty of 25%. Check this against the device reference manual and the STM32 Timer & PWM Calculator to confirm the arithmetic. Always verify the final PWM waveform in hardware, as startup timing, preload, updates, oscillator tolerance, output polarity, interrupts, and DMA can all affect the observed frequency.
Written by urgent.news from Dev.to's reporting — not their text. Machine-written — may contain errors; check the original before relying on it.
