My Nand2Tetris Journey #2 - Building Basic Chips And ALU

In Part 2 of his Nand2Tetris journey, the writer continued to build additional chips and an Arithmetic Logic Unit (ALU). Starting with the HalfAdder and FullAdder, the writer found that these components were relatively easy to construct by analyzing their respective truth tables. The HalfAdder was straightforward, while the FullAdder required combining logic gates and previously built chips.

After successfully creating the HalfAdder and FullAdder, the writer moved on to building the Add16 chip. Initially, summing 16 bits seemed challenging, but the writer soon realized that they could combine smaller adders and pass carry information to the next bit. The resulting 16-bit adder worked, albeit not in the most elegant manner.

Next, the writer tackled the Inc16 chip, which simply adds the value 1 to another number. By leveraging the Add16 chip, the writer was able to create Inc16 with relatively minimal effort. However, initially, the writer approached Inc16 in a less efficient manner, which led to a less visually appealing design.

The core component of Project 2 was the ALU, which required the writer to understand how to use multiplexers (Mux) to implement conditional logic. By recognizing that Mux could function as an "if" statement, the writer constructed the ALU using a combination of logic gates and previously built chips. The writer also learned the importance of reusing chips and applying bit slicing and fan-out techniques in hardware description language (HDL).

Initially, the writer struggled with deriving single-bit flags (zr and ng) from the ALU's 16-bit output. Through research and experimentation with fan-out, the writer discovered a method to access the required bits without directly slicing internal pins. With this newfound knowledge, the ALU finally functioned as intended, marking a successful completion of Part 2 of the Nand2Tetris journey.