Marvell VP pushes for DDR4 recycling for use in CXL memory, amid the worst DRAM shortage in years — company introduces three-tier AI memory infrastructure
Marvell has introduced a three-tier "AI memory infrastructure" portfolio, announced at FMS 2026 in Santa Clara on August 4.
Marvell's Vice President of Product Marketing, Khurram Malik, is advocating for the use of recycled DDR4 memory in CXL (Compute Express Link) memory, as the RAM market faces its most severe shortage in years. Within a three-tier AI memory infrastructure, DDR4 reuse ranks highest. The Bravera SC6 is a PCIe 6.0 x4 controller with 16 NAND channels and eight chip enables per channel, featuring 12 Arm Cortex-R82 cores and three Cortex-M7s.
Structera X, Structera S switch, and Photonic Fabric are part of Marvell's portfolio, with sampling starting in Q4 2026. Meta is a reference customer for this use case, utilizing an ASIC designed by the company, rather than Marvell's components. Meta has already been running recycled DDR4 behind CXL, cutting server counts by up to 25% for certain inference workloads.
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