Intel Xeon 7 'Diamond Rapids' comes with up to 256 P-cores, 1.28 GB of last-level cache — next-gen 18A-P CPU also brings AVX 10.2 and uses UCIe-S instead of EMIB
Intel has pulled back the curtain on its next-gen Diamond Rapids Xeon CPUs, packing up to 256 P-cores and 1.28 TB of last-level cache.
Intel has unveiled its upcoming Xeon 7, codenamed Diamond Rapids, CPUs, which boast up to 256 P-cores and 1.28 GB of last-level cache. The new CPUs are set to launch in the data center by 2027, introducing several advancements, including the new 18A-P process, UCIe interconnects, AVX 10.2, and the innovative fan-out fabric. While Intel has not detailed the core architecture, known as Panther Cove, in the Hot Chips 2026 presentation, a technical breakdown reveals how the Diamond Rapids chips are constructed, with compute tiles, or CBBs, stacking cores on top of the base tile housing the last-level cache.
Each core chiplet can accommodate up to 16 cores, and up to four chiplets can reside within a CBB. The chiplets are interconnected via a 3D crossbar, with Foveros Direct 3D used for bonding the compute tiles to the base tiles. Communication between the CBBs and base tiles occurs through 3D packaging and UCIe-S interconnects. Diamond Rapids also introduces a centralized memory and I/O subsystem, with memory speeds up to 16 channels at DDR5 and MRDIMMs speeds of up to 12,800 MT/s.
The integrated snoop filter in the memory fabric ensures cache coherency, removing the need for advanced packaging techniques like EMIB.
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