Samsung Develops New Technology to Overcome Interconnect Limits in AI Chips

Samsung Electronics has unveiled a groundbreaking technology capable of surmounting a significant physical constraint in semiconductor miniaturization. This innovation involves the manipulation of ruthenium, a forthcoming wiring material, by regulating its crystal orientation through the strategic application of carbon. The achievement was made possible by a collaborative effort between Samsung Advanced Institute of Technology (SAIT), Gwangju Institute of Science and Technology (GIST), and the Massachusetts Institute of Technology (MIT). Their findings were reported in the prestigious journal Science on August 13, 2024.

The semiconductor industry is in a relentless pursuit to produce chips that are not only more compact but also densely packed to cater to the demands of artificial intelligence and high-performance computing applications. However, the miniaturization of semiconductor circuits brings about a conundrum: as the size of these circuits decreases, the metal wiring connecting transistors also becomes thinner, thereby elevating the probability of electrons colliding with crystal boundaries during their passage.

This phenomenon results in higher resistance, which in turn can impede signal transmission, augment heat generation, and exacerbate power consumption, thereby restricting further enhancements in chip performance.

In response to this challenge, the research team devised an ingenious strategy. By integrating a carbon-based promoter into ruthenium, a material under consideration for next-generation semiconductor interconnects, they enabled the ruthenium crystals to grow and rearrange during heat treatment. This process yielded a thin film where over 99% of the crystals were aligned in a single orientation.

The aligned crystal structure effectively diminishes the obstacles encountered by electrons, thereby facilitating their smooth flow. When this technology was applied to nanoscale interconnects, it resulted in a line resistance that was approximately 45% lower than that of conventional ruthenium interconnects devoid of the carbon promoter.

Furthermore, the researchers successfully achieved a high level of crystal alignment on amorphous insulating films utilized in actual semiconductor manufacturing processes, thereby demonstrating the viability of this technology for complex three-dimensional semiconductor structures.

The research involved a team of 13 researchers, comprising 11 from SAIT. Three of the four co-first authors, including Lim Yong-chul and Ha Yun-ho, both Ph.D. researchers from SAIT, and Lee Young-min, a researcher from SAIT, are affiliated with Samsung Electronics. The fourth co-first author, Cho Yong-ryun, is associated with GIST's Central Research Facilities and Advanced Analysis Center.

Industry analysts believe that this technological breakthrough could play a pivotal role in meeting the stringent electrical performance requirements of next-generation semiconductor interconnects as wiring dimensions approach the 2-nanometer scale. If successfully commercialized, this technology has the potential to expedite electrical signal transmission and enhance power efficiency in advanced logic chips, thereby significantly boosting the performance of AI accelerators and other high-performance semiconductor applications.