Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip

Synopsys has announced the successful development of the first 3D PCIe 6.0 test chip, a 5nm device integrated into a face-to-face stacked package. This chip operates at a speed of 64 GT/s per lane, enabling data transfer rates of up to 128 GB/s across an eight-lane link using PAM4 signaling. The company achieved this milestone by deconstructing an existing 2D PCIe 6.0 test chip, incorporating through-silicon vias, and modifying the circuit design and signoff in accordance with 3D process design kits, as reported by Synopsys' blog.

In a 2.5D package, PCIe PHYs are typically positioned on the edges of the die near package I/O connections, which helps maintain short traces and manage attenuation and reflections. However, face-to-face hybrid bonding eliminates this layout option, forcing signals to travel through vias cut into the silicon to reach the PCIe PHYs, which are now facing away from the substrate they need to connect to.

Manmeet Walia, Synopsys' executive director of product management, explained the challenges of routing in 3D packaging. Due to the presence of active silicon in the vias, buffers must be added around them, making it difficult to place the vias directly beneath the PHYs. Additionally, electromigration and layout rules become more complex at this scale, as does the tradeoff between via count, bandwidth, and signal interference. Synopsys anticipates addressing these issues iteratively, design by design.

The shift towards PAM4 signaling, which transmits two bits per symbol, offers less tolerance for errors compared to the NRZ signaling used in PCIe 5.0. Fujitsu's Monaka processor, for instance, employs a different approach by stacking four N2 compute chiplets containing 144 Armv9 cores face-to-face on N5 SRAM chiplets using hybrid copper bonding, and placing memory controllers and PHYs for its 12 DDR5 channels on a separate, larger I/O die outside the bonded stack.

PCIe generations have historically been released roughly every five to seven years, but the pace has accelerated, with the Gen 8 specification expected in 2028 at 256 GT/s per lane. Walia also hinted at an upcoming evolution in 3.5D packaging, where PCIe PHYs will be removed from the bottom die and replaced with UCIe, relocating to a side chiplet on the interposer that functions as a multi-protocol hub for Ethernet, PCIe, and CXL.

However, no specific timeline has been provided for this development. Synopsys' blog highlights the company's focus on exploring angstrom-class process technologies for the top dies in these stacks.