RVA23 vs ARMv9 a Small Experiment

An experiment was conducted to compare the RISC-V and ARM instruction sets, focusing on static and dynamic code size, as well as decoding and execution efficiency. The test codebase was the chibicc C compiler, compiled using the chibicc compiler itself to simulate a realistic workload. Unoptimized scalar implementations of the mem* and str* functions from musl-libc were added to remove SIMD code from the comparison.

The results showed that RISC-V binaries were approximately 18% smaller than ARM binaries in terms of static code size. However, when comparing dynamic code size, the difference was more pronounced, with RVA23 needing to fetch 24% fewer bytes than ARMv9. Additionally, RVA23 fetched 21% fewer bytes than RVA22.

In terms of decoding efficiency, ARMv9 was found to be the clear winner, with about 6.5% fewer instructions to decode on average compared to RISC-V. This was attributed to ARM's more complex addressing modes, which required the CPU to break them into multiple micro-operations (uops). However, when adjusted for uops, the decoding efficiency between RISC-V and ARM binaries was found to be roughly equal.

In practical performance terms, both RVA22 and RVA23 were observed to execute faster than ARMv9. Interestingly, GCC binaries exhibited better performance than their respective clang counterparts, despite having a larger dynamic instruction and uop count. It is also noteworthy that clang showed inconsistent results between RVA23 and RVA22.

The experiment was conducted using QEMU user-mode emulation for QEMU and GEM5 micro-architectural simulator for ARM, which may have introduced some artifacts in the results. The GEM5 simulated time should be taken with caution, as it represents a theoretical comparison rather than a real-world scenario. Despite these limitations, the experiment suggests that RISC-V and ARM roughly match in the number of uops needed to feed their respective backends.

RISC-V benefits from its compressed instruction encoding, which allows it to fetch fewer bytes overall, but requires decoding more instructions directly into uops, with minimal instruction cracking. On the other hand, ARM decodes fewer instructions but cracks some of them into multiple uops due to its complex addressing modes.