Samsung Foundry updates process roadmap to move 1.4nm node to 2029 — high-NA EUV will enable 1nm-class and smaller nodes in 2030 and beyond

At the 2026 Next-Generation Lithography + Patterning Conference, Samsung Foundry unveiled an updated fabrication technologies roadmap, diverging significantly from the 2024 projection. Rather than prioritizing its SF1.4 node (1.4nm-class) for immediate release, Samsung will concentrate on enhancing its SF2 (2nm-class) manufacturing processes over the next three years.

Moving forward, Samsung intends to integrate High-NA EUV lithography tools for its SF1A (1nm-class) fabrication node, marking the first time the company has confirmed this plan.

The postponement of the SF1.4 node from 2027 to 2029 suggests that Samsung is taking a more measured approach, prioritizing the refinement of its SF2 family for improved yields and volumes. This strategy is influenced by Samsung's existing supply agreement with Tesla, which extends until 2033, necessitating a focus on meeting the needs of this major customer. Additionally, Samsung's plan to adopt pellicles for EUV photomasks may necessitate adjustments to its process recipes for future nodes.

Interestingly, Samsung's 1nm-class node will coexist with SF1.4+, an advanced version of SF1.4 employing an uncommon nomenclature. This indicates that Samsung will have both an innovative 1nm-class process utilizing High-NA EUV lithography and a technology grounded in proven Low-NA EUV methodologies and materials. Although Samsung has procured an ASML Twinscan EXE:5000 EUV lithography scanner with 0.55 numerical aperture projection optics for research purposes, it is not in a hurry to deploy High-NA EUV lithography for its 2nm-class and 1.4nm-class fabrication technologies. Samsung only plans to incorporate such a tool for its 1nm-class process around 2030.

Samsung's Master VP of Technology, Chang Min Park, at the conference, expressed that while the company is eager to apply High-NA EUV to mass production for nodes like 2nm and 1.4nm, the technology still requires further improvements. Park acknowledged that High-NA EUV may become essential from A10 and beyond and is actively engaging in joint development with various partners.

The primary challenge for chipmakers in adopting ASML's High-NA EUV tools lies in their substantially higher costs compared to Low-NA EUV systems, which can significantly increase fab and chip costs. Additionally, High-NA EUV scanners present a smaller exposure field, potentially necessitating die stitching for large chips and complicating designs.

These factors can diminish the performance advantage of High-NA EUV systems, which primarily minimize the need for multipatterning. Consequently, chipmakers must carefully assess when it is advantageous to employ costly single-patterning with High-NA EUV tools versus increasingly mature 0.33-NA EUV multi-patterning solutions. For instance, Intel plans to utilize High-NA EUV tools in some of its 14A technologies, while TSMC views High-NA EUV lithography as a potential technology for the 2030s.