{
  "id": 9413687,
  "title": "An Epyc trip to Venice: Everything we do and don't know about AMD's 256-core monster chip",
  "url": "https://urgent.news/2026/09/23/an-epyc-trip-to-venice-everything-we-do-and-dont-know-about-amds-256-9413687",
  "topic": "tech",
  "section": "Tech",
  "published": "2026-09-23T15:51:11.000Z",
  "source": {
    "name": "The Register",
    "slug": "the-register",
    "url": "https://www.theregister.com/systems/2026/09/23/an-epyc-trip-to-venice-everything-we-do-and-dont-know-about-amds-256-core-monster-chip/5298614"
  },
  "original_language": "en",
  "account": "AMD's Venice Epycs represent the chipmaker's most significant architectural shift in CPU design since the debut of Rome in 2019. The Venice product stack is shaping up to be the broadest CPU portfolio ever, spanning general purpose, HPC, AI, and eventually consumer platforms. However, AMD has not yet disclosed all the details about its 6th-gen Zen cores. Recently, AMD released a whitepaper that aims to counter Nvidia's narrative surrounding its Vera CPUs. This article will delve into the performance claims presented in the whitepaper and examine the architecture behind AMD's upcoming Venice CPU.\n\nAMD's 6th-gen lineup can be categorized into four main buckets: high-performance, enterprise, HPC, and AI. The high-performance parts, which will launch in 2026, are the main focus of this article, while the other categories will follow in 2027. The Venice Epyc platform is the centerpiece of AMD's announcement, featuring up to 256 cores, 16 channels of DDR5 memory, and 128 lanes of PCIe 6.0 connectivity.\n\nVenice comes in two flavors: density-optimized and frequency-optimized. The 256-core version, which is the density-optimized part, boasts a gigabyte of L3 cache onboard. The frequency-optimized version, on the other hand, has slightly fewer cores and cache, with 12 cores and 48 MB of L3 per chiplet. One notable change in Venice is the unified cache hierarchy, where all Zen 6 cores, regardless of type, share at least 4 MB of L3 cache each.\n\nA key difference between Venice and Intel's efficiency cores is that AMD retains the identical ISA (Instruction Set Architecture) for its Zen cores. The I/O dies in Venice have been updated to support faster PCIe 6.0 connectivity and the new CXL 3.1 standard, allowing customers to utilize memory god boxes for memory pooling and sharing. Additionally, Venice offers 16 channels of DDR5 memory running at 8000 MT/s or 12,800 MT/s, delivering a bandwidth of up to 1.6 TB/s, nearly three times that of Turin.\n\nAMD's Venice-X HPC-specific parts also share the SP7 socket but focus on delivering higher L3 cache per core, up to 12 MB or 1,152 MB per socket, using 3D V-Cache packaging technology. These chips are particularly well-suited for HPC workloads like computational fluid dynamics, finite element analysis, and electronic design automation. The Venice-X platform offers a substantial clock speed boost, reaching up to 5.15 GHz, thanks to the SRAM tile under the I/O dies.",
  "summary": "16 channels of DDR5, 5 GHz clock speeds, and support for CXL 3.1 memory god boxes? What's not to like?",
  "key_points": [],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 2,
    "also_reported_by": [
      {
        "outlet": "The Register Science",
        "title": "An Epyc trip to Venice: Everything we do and don't know about AMD's 256-core monster chip",
        "url": "https://urgent.news/2026/09/23/an-epyc-trip-to-venice-everything-we-do-and-dont-know-about-amds-256",
        "published": "2026-09-23T15:51:11.000Z"
      }
    ]
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}