{
  "id": 8232318,
  "title": "Ashwini Vaishnaw's Big Bet: India Wants 200 Chip Design Startups, Not Just Fabs",
  "url": "https://urgent.news/2026/09/18/ashwini-vaishnaws-big-bet-india-wants-200-chip-design-startups-not",
  "topic": "tech",
  "section": "Tech",
  "published": "2026-09-18T10:05:37.000Z",
  "source": {
    "name": "YourStory",
    "slug": "yourstory",
    "url": "https://yourstory.com/2026/09/india-chip-design-startups-semicon-2-0-msme"
  },
  "original_language": "en",
  "account": "India's electronics and information technology minister, Ashwini Vaishnaw, announced ambitious plans to boost the country's chip design sector during a speech at the SEMICON India 2026 conference. The government aims to support over 200 deep-tech chip design startups, a significant increase from the 105 startups that emerged during the first phase of semiconductor incentives, Semicon 1.0. Vaishnaw emphasized that Semicon 2.0, with an investment of Rs 1,27,500 crore, would focus on six key pillars - design, materials and machines, additional fabrication plants, expanded assembly, testing, marking and packaging (ATMP) capacity, research and development, and talent development. One of the critical measures to support startups is the shared access to electronic design automation (EDA) tools, which have traditionally been prohibitively expensive for young design companies. By providing shared access through the Centre for Development of Advanced Computing, more than 105 startups have been able to enter the chip design space, with 20 of them securing venture capital funding. The government's strategy also aims to leverage India's strong precision manufacturing ecosystem, comprising small and medium enterprises, to create a strong foundation for the semiconductor industry. As part of this initiative, the government is developing a multi-level skilling framework, including a 240-hour Level 1 course for students to gain engineering-level capabilities, as well as a dedicated Precision Manufacturing Institute. Additionally, the government aims to train 85,000 semiconductor design engineers over ten years, with around 70,000 engineers trained in the first four years. The clean room technician target of one lakh under Semicon 2.0 may need to be revised upward due to industry demand. While the success of Semicon 2.0's scale-up will depend on the impact of its shared infrastructure and phased skilling approach, the government's investment in chip design startups and the MSME manufacturing base signals a significant bet on India's deep-tech chip design sector.",
  "summary": "As India firms up its second semiconductor phase, small design startups and MSME manufacturers are being positioned as the ecosystem's backbone.",
  "key_points": [],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}