{
  "id": 47349,
  "title": "AMD's new Zen 6 chips will have a low-power core built from five different generations of Zen",
  "url": "https://urgent.news/2026/08/02/amds-new-zen-6-chips-will-have-a-low-power-core-built-from-five",
  "topic": "science",
  "section": "Science",
  "published": "2026-08-02T14:12:00.000Z",
  "source": {
    "name": "TechSpot",
    "slug": "techspot",
    "url": "https://www.techspot.com/news/113321-amd-new-zen-6-chips-have-low-power.html"
  },
  "original_language": "en",
  "account": "AMD has unveiled an innovative approach for its upcoming Zen 6 processors, introducing a new low-power core built from elements of several previous Zen generations instead of a singular architecture. This revelation was highlighted in a recent Linux kernel patch, detailing how the system recognizes and handles these cores. The patch emphasizes that these low-power cores are distinct enough to require a separate classification within user space. Previously, they were lumped together with AMD's existing compact \"C\" cores, but now they are handled differently. The system requires recognition of these cores in user space, as they currently appear as \"unknown\" in CPU topology. Moreover, the patch specifies that these cores should scale performance using amd_get_highest_perf() on supported AMD and Hygon chips, rather than a fixed CPPC_HIGHEST_PERF_PERFORMANCE limit. The construction of these cores is a hybrid design that amalgamates multiple Zen generations. According to leaker InstLatX64, the design includes a Zen 6 instruction set, Zen 5 microarchitecture, Zen 4 floating-point unit, Zen 3 L2 cache, and Zen 2 L3 cache. By reusing and combining existing components, AMD aims to improve efficiency while minimizing development time and complexity. These low-power cores will coexist with AMD's current Performance and Efficiency cores, forming a three-tier system. Performance cores tackle high-clock workloads, Efficiency cores are smaller and optimized for lower power use, while the new low-power cores target light workloads where power minimization is paramount. This design is similar in purpose to Intel's low-power efficiency cores but structured differently. The potential advantage lies in mobile devices, where these cores could offload light tasks, reducing power consumption and extending battery life. However, the success of this design hinges on the software's ability to manage and assign workloads across different core types. More data on performance and efficiency of these cores is lacking, and it remains unclear how well this hybrid architecture would scale under real-world workloads. The unconventional design and its success will depend on the harmonious collaboration between hardware and software layers. AMD is also releasing Zen 6 server chips, with desktop versions anticipated later this year. However, limited PC shipments and higher memory prices due to AI demand may impact the market, potentially limiting adoption if buyers postpone upgrading to new hardware. Despite these challenges, the concept of creating a core from a blend of proven parts represents a significant shift in AMD's chip design strategy. By assigning specialized roles to different core types, AMD may gain greater flexibility in designing chips for power-sensitive devices.",
  "summary": "Patch notes that the system needs a way to properly identify these low-power cores in user space, since they currently show up as \"unknown\" in the CPU topology. Read Entire Article",
  "key_points": [
    "AMD introduces low-power cores built from five different Zen generations",
    "New cores require separate classification in user space"
  ],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}