{
  "id": 4653745,
  "title": "Nvidia revives Rubin CPX chip program with 2027 launch planned, analyst says",
  "url": "https://urgent.news/2026/08/31/nvidia-revives-rubin-cpx-chip-program-with-2027-launch-planned",
  "topic": "tech",
  "section": "Tech",
  "published": "2026-08-31T14:16:22.000Z",
  "source": {
    "name": "Investing.com",
    "slug": "investing-com",
    "url": "https://www.investing.com/news/stock-market-news/nvidia-revives-rubin-cpx-chip-program-with-2027-launch-planned-analyst-says-93CH-4882972"
  },
  "original_language": "en",
  "account": "Nvidia has reintroduced its Rubin CPX chip program, ending speculation that it had been abandoned, according to Ming-Chi Kuo of TF International Securities. Production of the updated CPX chips is slated to commence in the first quarter of 2027. Enhanced GPU specifications and a revised rack design characterize the revised Rubin CPX. Each CPX GPU is capable of delivering computing performance comparable to the Rubin GPU, with a maximum power rating of 2,300 watts. The memory configuration uses 168 GB of HBM4, a departure from the 288 GB memory in the previous CPX version and the 128 GB of GDDR7 in an earlier iteration. The new design employs a separate MGX ETL rack, distinct from the Rubin's shared rack space. Customers may opt for configurations ranging from 64 to 256 CPX GPUs, with each set of 64 GPUs constituting a module comprising eight compute trays containing eight GPUs each and a switch tray. NVLink facilitates communication among eight CPX GPUs within a tray, delivering 1 to 1.5 TB per second of NVLink bandwidth per CPX, contrasted with 3.6 TB per second for each Rubin GPU. Cross-module connections utilize OSFP optical links. Nvidia mandates a 1:1 ratio between CPX and Vera Rubin NVL72 for optimal performance. The CPX assumes responsibility for prefill tasks and builds the KV cache, which is transferred to Rubin through Ethernet RDMA for decode processing. Over 50% of contemporary AI inference workloads revolve around input context processing and KV cache construction. Each eight-CPX tray encompasses approximately 1.34 TB of HBM4 memory.",
  "summary": null,
  "key_points": [],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}