{
  "id": 306700,
  "title": "Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute",
  "url": "https://urgent.news/2026/08/08/hardware-researcher-spins-up-cpu-deoptimization-project-to-find-the",
  "topic": "tech",
  "section": "Tech",
  "published": "2026-08-08T11:20:00.000Z",
  "source": {
    "name": "Tom's Hardware",
    "slug": "tom-s-hardware",
    "url": "https://www.tomshardware.com/pc-components/cpus/hardware-researcher-spins-up-cpu-deoptimization-project-to-find-the-slowest-machine-code-worst-offender-takes-198-billion-cycles-to-execute"
  },
  "original_language": "en",
  "account": "Hardware researcher Christopher Domas has embarked on a project to identify the slowest single x86 instruction, creating a hall of shame showcasing the worst offenders. The winner of this endeavor is the fxrstor64 instruction, which took an astonishing 62 seconds, or over 198 billion cycles, to complete its task. Domas achieved this by first locating a high-latency area in the internal PCIe fabric, then forcing the CPU to load a 512-byte state from Memory-Mapped I/O, essentially processing all those 512 bytes at their slowest possible pace. To further extend the execution time, he depleted the fabric while the load was in flight, overwhelming the CPU's PCIe root complex and causing the state restore to queue behind frivolous read operations. The next step in the project is to employ the AMX instructions available in Intel's Sapphire Rapids, which could potentially cause the instruction to hang for more than 1 trillion cycles. Domas has also planned ARM and RISC-V leaderboards, and the x86 leaderboard is now available on GitHub. The project aims to shed light on the slowest machine instructions, rather than optimizing for speed, and the rankings are based on how you manipulate the instruction rather than the instruction itself.",
  "summary": "One hardware researcher, Christopher Domas (@xoreaxeaxeax on GitHub), is taking a different approach with the CPU Deoptimization leaderboard, which looks not to make Assembly instructions run as fast as possible, but as slow as possible to find the single instruction with the highest latency.",
  "key_points": [
    "Christopher Domas leads project to find slowest x86 instruction",
    "fxrstor64 instruction takes 62 seconds, 198 billion cycles",
    "Project aims to highlight slowest machine instructions"
  ],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}