{
  "id": 18982272,
  "title": "Playing with the STM32MP2",
  "url": "https://urgent.news/2026/11/08/playing-with-the-stm32mp2",
  "topic": "tech",
  "section": "Tech",
  "published": "2026-11-08T17:12:00.000Z",
  "source": {
    "name": "Lobsters",
    "slug": "lobsters",
    "url": "https://serd.es///2026/11/08/playing-with-stm32mp2.html"
  },
  "original_language": "en",
  "account": "Apology: this account is delayed. Initial writing took place around December 2025, but a security bug required immediate silence until ST could provide an advisory. Afterward, the account was delayed by other projects. Dedicated followers of my work will know I enjoy pairing STM32 microcontrollers with FPGAs, achieving impressive results such as near-Gbps Ethernet bandwidth between the MCU and FPGA. However, one limitation exists: the STM32H7 FMC requires many pins (over 30) which are not conveniently located, making routing on low-cost boards challenging. My ideal MCU would be a 1 GHz Cortex-M7 or M85 on TSMC 28LP, with ample RAM, an RGMII MAC, multiple FPGA-style I/O banks, and an AXI Chip2Chip SERDES block for direct integration with FPGA-based peripherals using only two differential pairs. While no such device exists, the STM32H735 paired with an external FPGA over FMC came close, but routing on low-cost batch fab design rules proved difficult. The STM32H735 had lower CPU speed (480 MHz) and was a stopgap solution rather than a full fix. Other STM32H7 parts, like the H75x line, are available in a smaller package (0.8mm) suitable for batch fab design, but their CPU speed is 480 MHz, merely postponing the issue rather than solving it. Would a fast M7 with PCIe have been better? Perhaps, but there are no such devices. ARM Cortex-R processors with PCIe are an option, but transitioning from familiar STM32 peripherals would be a significant challenge. Additionally, many of these parts lack crypto acceleration or have cryptographically obscure documentation, which is a significant drawback for me. However, the STM32MP2 line caught my attention. This applications processor SoC features dual Cortex-A35, auxiliary processors like M33 and M0+, a GPU/NPU, and a 5 Gbps SERDES with PIPE interface that can operate as PCIe gen1/2 x1 or USB 3, depending on the internal protocol IP connected. It also retains most of the familiar STM32 peripherals, including AES-GCM and TRNG IPs, for which I have existing drivers and documentation. It offers far more computing power than I require and provides a playground for future designs needing more processing power. The PCIe interface offers the potential to map FPGA memory easily into firmware via only two differential pairs. However, the STM32MP2 is tailored for Linux operation, and the vendor's BSPs include a plethora of u-boot, TrustZone, etc. functionalities that I did not require. For a simple RTOS or an endless loop (doStuff());, I decided to explore whether the MP2 could be configured as a high-speed MCU with unique peripherals like PCIe and LPDDR PHYs, which are not commonly found in regular microcontrollers. This involved purchasing a STM32MP257 development board, adding a linker script and header to stm32-cpp for the addresses of the peripherals that shared the same register interface as other STM32 components. The main difference was the image base address being in SRAM instead of flash. Building a simple LED blinky firmware for the Cortex-M33 auxiliary core and loading it over JTAG proved relatively straightforward, achieving Achievement #1: communication with the chip and manipulation of registers. The subsequent milestone was to boot the same blinky from flash. After researching example code and wikis, I determined the necessary boot ROM configurations to load the firmware from flash and execute it. This led to Achievement #2: the ability to boot the chip from nonvolatile memory without relying on JTAG for every boot cycle. While preparing the FSBL image, several considerations must be kept in mind: this firmware booted in \"M33-TD\" mode, where the boot ROM immediately transfers control to the M33, which holds full TrustZone privileges. I opted for this mode over \"A35-TD\" primarily because I wanted to gradually bring up the platform, avoiding the complexity of setting up a bare-metal Cortex-A processor at the outset. Further details regarding the process will follow.",
  "summary": null,
  "key_points": [
    "STM32MP2 SoC features dual Cortex-A35 processors and a 5 Gbps SERDES.",
    "STM32MP2 tailored for Linux with familiar STM32 peripherals and crypto acceleration.",
    "Developer configured STM32MP2 as high-speed MCU with PCIe and LPDDR PHY support."
  ],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}