{
  "id": 15444912,
  "title": "The RISC vs CISC debate is dead because both sides stole each other's best ideas",
  "url": "https://urgent.news/2026/10/18/the-risc-vs-cisc-debate-is-dead-because-both-sides-stole-each-others",
  "topic": "culture",
  "section": "Culture",
  "published": "2026-10-18T16:00:19.000Z",
  "source": {
    "name": "XDA Developers",
    "slug": "xda-developers",
    "url": "https://www.xda-developers.com/risc-cisc-debate-dead-both-side-stole-best-ideas/"
  },
  "original_language": "en",
  "account": "The RISC vs CISC debate has been rendered obsolete, as both camps have appropriated each other's most effective concepts. Typically, processors fall into two categories: x86, classified as CISC in PCs, and Arm-based processors, deemed RISC in smartphones. Although these labels signify certain aspects of the instruction set, they offer limited insight into the hardware's inner workings. Over the past three decades, high-performance x86 cores have embraced RISC principles, while advanced Arm cores now incorporate CISC techniques.\n\nDespite the initial perception that Arm's efficiency stems from its RISC architecture, the crucial differences between RISC and CISC lie in their design philosophies. While the instruction set alone cannot explain these disparities, it is essential to recognize that both camps have largely converged on practical implementations. The complexity of x86 instruction encoding does incur costs, but these expenses are insufficient to account for the performance and efficiency advantages observed in Arm-based processors.\n\nIntel's initial 8086, introduced in 1978, employed microcode to manage the execution of numerous x86 instructions, with each instruction supported by a micro-instruction in an on-chip ROM. Conversely, RISC advocates, led by John Hennessy and David Patterson, opted for a contrasting approach. They aimed to create simpler instructions executable directly by hardware, thereby concentrating resources on registers and instruction caches. The RISC philosophy yielded superior performance, as demonstrated by the MIPS and RISC-I designs developed at Stanford and Berkeley in the early 1980s. Hennessy and Patterson later highlighted a DEC comparison, where CISC required fewer instructions per program but significantly more cycles per instruction, resulting in a fourfold speed advantage for RISC in comparable technology.\n\nIntel and AMD have since adopted microcode updates for existing chips, acknowledging the limitations of solely relying on instruction set design. By the late 1980s, researchers recognized the diminishing relevance of CISC, with Intel's Pentium Pro (1995) marking a pivotal shift. The Pentium Pro introduced a five-stage pipeline that could sustain one simple instruction per clock for certain operations, while more complex instructions consumed additional cycles. This evolution culminated in the mid-1990s, when Intel's Nx586 and AMD's K5 processors began translating x86 instructions into simpler internal operations, effectively merging RISC-like techniques within the CISC framework.",
  "summary": "You may have heard that x86 is RISC on the inside, but what does that mean exactly?",
  "key_points": [],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}