{
  "id": 10942470,
  "title": "The state of agentic AI in chip design tools in 2026",
  "url": "https://urgent.news/2026/09/30/the-state-of-agentic-ai-in-chip-design-tools-in-2026",
  "topic": "ai",
  "section": "AI",
  "published": "2026-09-30T12:20:00.000Z",
  "source": {
    "name": "Tom's Hardware",
    "slug": "tom-s-hardware",
    "url": "https://www.tomshardware.com/tech-industry/semiconductors/the-state-of-agentic-ai-in-chip-design-tools-in-2026-cadence-synopsys-and-siemens-all-pitch-autonomous-engineers"
  },
  "original_language": "en",
  "account": "In 2026, three leading chip design software companies, Cadence, Synopsys, and Siemens EDA, have significantly enhanced their Electronic Design Automation (EDA) agents. These AI-driven agents now claim remarkable improvements in various stages of chip design, from specification to verified RTL (Register Transfer Level) code.\n\nCadence showcased its advanced \"bounded Level 5\" super agent, ChipStack, at Computex on June 1, stating it had reached Level 5 autonomy in a single domain, with most of its technology at an \"advanced Level 4\" level. Synopsys demonstrated its spec-to-RTL workflow in March, claiming Level 5 capabilities for its long-horizon agents. Siemens introduced its self-verifying agent, Fuse EDA AI, on March 16, with additional self-checking loops announced on July 26.\n\nWhile these claims of progress are noteworthy, the actual performance improvements remain ambiguous due to varying measurement criteria and the absence of standardized evaluation metrics. The claimed gains in speed are often based on vendors' or customers' figures, frequently accompanied by \"up to\" or \"early evaluation\" disclaimers. Moreover, the evaluation baselines differ for each company, making direct comparisons challenging.\n\nThe AI agents in chip design tools primarily rely on established technologies with known outputs. Progress has been measured in three primary generations - reinforcement learning in 2020, generative AI capabilities in 2023, and an open agentic AI stack from 2025 to 2026. However, all decisions made by these agents must be validated by existing deterministic EDA engines. The agents focus on evaluating intermediate results and determining subsequent actions, creating a loop where the agent's proposal is examined by an existing engine like Xcelium, Jasper, Questa, Calibre, or Fusion Compiler.\n\nThe autonomy of these agents varies, with Cadence labeling its progress from Level 1 to Level 5 autonomy, while Synopsys employs a similar L framework - ranging from single agent actions on individual design steps to more complex, multi-agent decision-making. The ultimate goal for Synopsys remains maintaining human engineers in the loop, ensuring human oversight throughout the design process.",
  "summary": "Cadence, Synopsys, and Siemens all offer agentic AI for chip design, largely built on Nvidia's stack, with varying claims of autonomy.",
  "key_points": [],
  "editors_take": null,
  "illustration": null,
  "coverage": {
    "outlets": 1,
    "also_reported_by": []
  },
  "ai_generated": true,
  "disclaimer": "Summaries, key points and the editor’s take are written by software from other outlets’ reporting and may contain errors — always check the linked original."
}